1. Field of the Invention
The present invention relates to an insulated gate semiconductor device, and more particularly to an insulated gate semiconductor device that contributes to a reduction in on-state resistance.
2. Description of the Related Art
An insulated gate semiconductor device having a trench structure is known which includes trenches in a grid pattern as seen in plan view. This technology is described for instance in Japanese Patent Application Publication No. 2010-238796.
Also, a reduction in on-state resistance is an important issue for the insulated gate semiconductor device having the trench structure, and one approach therefor is that cells are becoming increasingly finer. As an example of finer cells, known is a structure in which an interlayer dielectric that provides insulation between a gate electrode buried in a trench and a source electrode provided on a substrate surface is buried in the trench, so that the substrate surface is flattened. In this structure, the trenches are formed in stripes in the substrate as seen in plan view, and a source region is arranged to cross the trenches. This technology is described for instance in Japanese Patent Application Publication No. 2009-224458.
A configuration in which the trenches provided in the substrate and the gate electrodes buried in the trenches (hereinafter called generically trench gates) are in the form of stripes and an n type semiconductor region (i.e. a source region) and a p type semiconductor region (i.e. a base region or a body region) are arranged to cross the trench gates at right angles, as disclosed in Japanese Patent Application Publication No. 2009-224458, enables reducing a distance between the trench gates as compared to a configuration in which the trench gates are formed in the grid pattern as disclosed in Japanese Patent Application Publication No. 2010-238796, or specifically enables reducing a pitch of the trench gates to ⅓ of that of the trench gates in the grid pattern.
Also, the pattern of Japanese Patent Application Publication No. 2009-224458 enables reducing the distance between the trench gates and hence reducing the on-state resistance, as compared to a configuration in which the trench gates are in the form of stripes and the n type semiconductor region and the p type semiconductor region are arranged next to each other in parallel to adjacent trench gates between the adjacent trench gates.
However, it is known that, in the structure of the trench gates in the form of stripes as described above, voids occur in polycrystalline silicon filled into the trenches, and the occurrence of the voids can possibly cause characteristic variations (e.g. on-state resistance variations, threshold voltage (Vp) variations, and forward voltage (Vf) variations) or the like.
Also, there are demands for the reduction in the on-state resistance for further improvements in the characteristics.